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| Ordering number: EN4876B Bi-CMOS LSI LV2105V 530 MHz PLL Frequency Synthesizer LSI Overview The LV2105V is a PLL frequency synthesizer Bi-CMOS LSI that provides low-voltage operation and low current drain, and that is suitable for use in a variety of radio equipment. Package Dimensions unit: mm 3178-SSOP16 [LV2105V] Functions . PLL function . Data input by serial transfer (CCB format) . Input amplifier for crystal oscillation circuit . Data output port Features . Low operating voltage: (V = 2.5 to 5.5 V) . Low current drain (5.5 mA) . Compact package (SSOP16, 0.65 mm pitch) . VCO band switching data output port on chip . Data can be input while in power saving mode . Data input pin high level can be input at V or higher . Independent setting of CP ON/OFF (high impedance) CC CC SANYO : SSOP16 . . possible CCB is a trademark of SANYO ELECTRIC CO., LTD. CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. Specifications Absolute Maximum Ratings at Ta = 25 C Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Maximum output current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VIN max(1) VIN max(2) VOUT max(1) VOUT max(2) IOUT max Pd max Topr Tstg VCCR, VCCD CE, CL, DI XIN, TEST PDP PDN, OUT, PE PDP 114 x 76 x 1.6 mm When using glass epoxy board 3 Conditions Ratings -0.3 to +6.0 -0.3 to +6.0 -0.3 to VCC+0.3 -0.3 to +9.0 -0.3 to VCC+0.3 0 to +1.0 230 -40 to +85 -50 to +125 Unit V V V V V mA mW C C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN D3095HA(II) No.4876-1/7 LV2105V Pin Assignment Allowable Operating Ranges at Ta = -40 to +85 C Parameter Supply voltage High-level input voltage Low-level input voltage Output voltage Input frequency Input amplitude Crystal oscillation condition Symbol VCC VIH VIL VOUT fIN(1) fIN(2) VIN(1) VIN(2) Xtal Conditions VCCR, VCCD CE, CL, DI CE, CL, DI PDP XIN: Sine wave capacitive coupling PI: Sine wave capacitive coupling XIN: Sine wave capacitive coupling PI: Sine wave capacitive coupling XIN, (XOUT) Min 2.5 VCCR x 0.7 0 0 5 100 -12 -18 5 Typ Max 5.5 5.5 +0.6 +7.0 22 530 +10 0 13 Unit V V V V MHz MHz dBm dBm MHz Electrical Characteristics at Ta = 25 C, VCCR = 3.0 V, VCCD = 3.0 V Parameter Symbol VOL(1) VOL(2) VOL(3) VOL(4) VOH(1) VOH(2) IOFF(1) IOFF(2) ICP IH(1) IH(2) IH(3) IL(1) IL(2) IL(3) Rf ICC(1) ICC(2) Conditions PDP: IO = 0.5 mA PDN: IO = 0.5 mA PE: IO = 0.5 mA OUT: IO = 2.0 mA PE: IO = -0.5 mA PDN: IO = -0.5 mA PDP: VO = 3.0 V CP: VO = 1.5 V CP: VO = 1.5 V CE, CL, DI: VI = 3.0 V XIN: VI = 3.0 V TEST: VI = 3.0 V CE, CL, DI: VI = 0 V XIN: VI = 0 V TEST: VI = 0 V XIN VCCR, VCCD: *1 VCCR, VCCD: *1 min typ max 0.5 0.5 0.5 0.5 Unit V V V V V V A nA mA A A A A A A M mA mA Low-level output voltage High-level output voltage Output off leak current C.P output current High-level input current VCC -0.5 VCC -0.5 1.0 100 11 5.0 4.3 5.0 5.0 4.3 5.0 9.0 0.6 4.0 2.3 7.5 3.0 Low-level input current Internal feedback resistance Supply current PS supply current 2.3 3.0 1.0 5.5 0.4 *1: XIN = 12.8 MHz, 10 dBm, PI = 400 MHz, 0 dBm, other input pins = 0 V, output, I/O pins = OPEN CP OFF No.4876 -2/7 LV2105V Equivalent Circuit Block Diagram Serial Data (PLL Control Data) Configuration 1) Mode 1: Latch-1 data (Reference divider, other data) Mode data Control data No.4876 -3/7 LV2105V 2) Mode 2: Latch-2 data (Programmable divider data) Mode data Control data Serial Data (Transfer) Timing Internal data Serial Data Explanation Pin No. (1) Control block/data Reference frequency data FR0 to FR1 . . Internal block Data that sets the division ratio of the reference divider. Binary value with FR0 as the LSB. However, the settable division ratio factor is up to 4095. (Actual division ratio) = (Set division ratio) (x2: when DIV is ``1'') Data that sets whether to use 1/2 DIV or to enter the through state. (2) 1/2 divider data DIV DIV data Item 0 Through 1 1/2 DIV Continued on next page. No.4876 -4/7 LV2105V Continued from preceding page. Pin No. (3) Control block/data Power save data PS . Internal block Data that sets the power save mode on or off PS data Item 0 Power save mode 1 Normal operation (4) Output port data OUT . Data that sets the output of the output port OUT data OUT Pin 0 Low 1 High (5) Charge pump ON/OFF data CP . Data that sets whether to operate the charge pump or to implement high impedance. CP data Item 0 High impedance 1 Normal operation (6) (7) LSI test data TS1 Programmable divider data FP0 to FP16 . . LSI test mode switch. Set TS1 = 0. Normally, the TEST pin is connected to GND. Data that sets the division ratio of the programmable divider. Binary value with FP0 as the LSB. However, the settable division ratio factor is up to 131071. Pin Functions Pin Name 1 2 3 4 5 6 7 8 9 10 XIN CL DI CE VCCR PI GND R TEST CP PDP Data input pin Data input pin Data input pin ECL block power supply pin Comparison signal input pin ECL block GND pin LSI test pin. Must be connected to GND. Built-in charge pump output pin Phase comparator output for an external charge pump. If not to be used, connect to GND. Phase comparator output for an external charge pump. GND pin for circuits except the ECL block Power supply pin for circuits except the ECL block Phase error output pin for phase comparator Output port pin for switching external SW. Output pin for Xtal oscillation CMOS output BIP NPN open-collector output CMOS output CMOS, No pull-down BIP CMOS, Nch open-drain output BIP input Pin Function Reference signal input pin (Xtal oscillation pin) CMOS input CMOS, No pull-down CMOS, No pull-down CMOS, No pull-down I/O Style 11 12 13 14 15 16 PDN GND D VCCD PE OUT XOUT CMOS output No.4876 -5/7 LV2105V Sample Application Circuit No.4876 -6/7 LV2105V No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1995. Specifications and information herein are subject to change without notice. No.4876 -7/7 |
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